Tuning IDS for Multicore CPUs

Greetings All, I am hoping someone can provide some guidance concerning the tuning of IDS for multicore CPU architectures. Currently, I have a number Sun Ultra Sparc III machines that will be replaced with multicore Ultra Sparc IV + boxes. I have been unable to locate any specific guidance in this area. IBM Tech support said they do not offer any direction for this and suggested to treat each core as a physical processor. Given we tend to run 2 CPU VPs per processor, with blazingly fast performance on the Ultra Sparc IIIs, this configuration does not seem to fare anywhere near as well with the multicore CPUs. Pruning the number of CPU VPs to 1/2 the number of cores seems to fare much better. Perhaps this has to do with L2 cache? Does anyone have any insight into this? Thanks,

the_omegamon@yahoo.com wrote: > Greetings All, > > I am hoping someone can provide some guidance concerning the tuning > of > IDS for multicore CPU architectures. Currently, I have a number Sun > Ultra > Sparc III machines that will be replaced with multicore Ultra Sparc IV > + boxes. > I have been unable to locate any specific guidance in this area. IBM > Tech > support said they do not offer any direction for this and suggested to > treat > each core as a physical processor. Given we tend to run 2 CPU VPs > per > processor, with blazingly fast performance on the Ultra Sparc IIIs, > this > configuration does not seem to fare anywhere near as well with the > multicore > CPUs. Pruning the number of CPU VPs to 1/2 the number of cores seems > to > fare much better. Perhaps this has to do with L2 cache? Does > anyone have > any insight into this? > > Thanks, > The "official" general rule is one CPU VP per single core processor, but as you mention, it may be better with other settings. A rule of thumb for multi core processors is two CPU VPs per three cores. Again it depends - partly on the architecture (fx shared L2 cache) and partly (probably most) on the usage of IDS. One of the ideas with IDS dynamic scalable architecture (DSA) is to avoid context switching, because thread switching has a lower cost than process switching. With only one CPU VP per processor context switching is minimized. I think, the best advice is to experiment with the number of CPU VPs, while the system is in production; use 'onmode -p +/-# CPU' to change dynamical the number of CPU VPs. Monitor the processor idle time (vmstat or sar) and monitor the length of the ready queue (onstat -g rea).